1) Field of the Invention
The present invention relates to a technology for detecting a stop of oscillation of an internal oscillation circuit of an electronic device.
2) Description of the Related Art
Normally, an electronic device including an internal oscillation circuit is provided with an oscillation-stop detection system. As for a clock driven by a battery, for example, a clock integrated-circuit (IC) employs a crystal oscillation circuit. While the crystal oscillation circuit is in an oscillation state, a regulated voltage obtained by dropping a power supply voltage of the clock IC using a regulator is used as a power supply of the crystal oscillation circuit. This is intended to reduce current consumption.
On the other hand, when restarting the crystal oscillation circuit that is in an oscillation stop state, the power supply voltage of the clock IC is used for a prompt and certain start of the oscillation. After restarting the oscillation, the crystal oscillation circuit is driven by the regulated voltage. For this mechanism to work, the oscillation-stop detection system detects a stop of oscillation of the crystal oscillation circuit, and generates a signal necessary to control switching of the power supply for driving the crystal oscillation circuit.
FIG. 11 is a circuit diagram of a configuration of a conventional oscillation detecting circuit. In the oscillation detecting circuit 100 shown in FIG. 11, an N-channel MOS transistor 101 is repeatedly turned on and off based on a potential of an oscillation signal CK supplied from an oscillation circuit (not shown). A capacitor 102 is connected between a high voltage power supply potential VDD and a low voltage power supply potential VSS and charged while the N-channel MOS transistor 101 is turned on. In addition, the capacitor 102 is slightly discharged by a leak current carried across a pull-up resistor 103 while the N-channel MOS transistor 101 is turned off. However, the capacitor 102 is charged again when the N-channel MOS transistor 101 is turned on. By repetition of the charge and discharge, a potential of an input terminal of an inverter 104 is stabilized to the low voltage power supply potential VSS.
Accordingly, while the oscillation signal CK is supplied, a potential of an oscillation-stop detection signal OSCST output from the inverter 104 is at a “high (H)” level at which the potential thereof is relatively high. If the supply of the oscillation signal CK is stopped in this state, the capacitor 102 is then continuously discharged according to a time constant CR and the potential of the input terminal of the inverter 104 starts rising toward the high voltage power supply potential VDD, accordingly. If the potential of the input terminal of the inverter 104 is higher than a threshold of the inverter 104, the potential of the oscillation-stop detection signal OSCST output from the inverter 104 is switched from the “H” level to a “low (L)” level at which the potential thereof is relatively low. In this way, the oscillation detecting circuit 100 detects whether the oscillation circuit oscillates based on the potential of the oscillation-stop detection signal OSCST.
The conventional oscillation detecting circuit requires the pull-up resistor 103 to have a high resistance of about several hundreds of megaohms to about several gigaohms so as to set a discharge time to an appropriate time. However, if such a high resistance is formed within an IC chip, the following problems occur. First, an occupied area of the resistance relative to the IC chip is extremely large, resulting in an increase in a size of the IC chip. Second, because of a large fluctuation in manufacturing process, an absolute accuracy of the resistance is deteriorated. Accordingly, a desired discharge time cannot be obtained and the oscillation detecting circuit cannot often accurately detect whether the oscillation circuit oscillates. Furthermore, the resistance tends to change due to an influence of an external environment such as a light and a temperature. For this reason, for example, when the resistance decreases, a discharge current then increases and the oscillation detecting circuit may possibly erroneously detect that the oscillation of the oscillation circuit is stopped.
Considering these problems, an oscillation detecting circuit 200 configured as shown in FIG. 12 is proposed (see, for example, Japanese Patent Application Laid-open No. 2000-332585 (FIG. 1)). The oscillation detecting circuit 200 includes a constant-current source 201 and a current-mirror circuit as units that discharge the capacitor 102. One P-channel MOS transistor 202 that constitutes the current-mirror circuit is connected to the constant-current source 201 and applies a constant current thereto. The other P-channel MOS transistor 203 that constitutes the current-mirror circuit applies a discharge current proportional to the constant current carried across the one P-channel MOS transistor 202.
In the oscillation detecting circuit 200, similarly to the oscillation detecting circuit 100 configured as shown in FIG. 11, the N-channel MOS transistor 101 is repeatedly turned on and off while the oscillation signal CK is supplied thereto, and the charge and the slight discharge of the capacitor 102 are repeated. In this state, the potential of the input terminal of the inverter 104 is stabilized to the low voltage power supply potential VSS, and the “H” level oscillation-stop detection signal OSCST is output from the inverter 104. When the oscillation is stopped, the capacitor 102 is continuously discharged by the discharge current carried across the other P-channel MOS transistor 203. The potential of the input terminal of the inverter 104 is thereby made higher than the threshold of the inverter 104, and the “L” level oscillation-stop detection signal OSCST is output from the inverter 104.
With the configuration in which the pull-up resistor is used as the unit that discharges the capacitor (see FIG. 11), however, the oscillation detecting circuit requires the pull-up resistor to have a high resistance of about several hundreds of megaohms to about several gigaohms so as to set the discharge time at the appropriate time. If such a high resistance is formed within an IC chip, the two problems described above occur. The oscillation detecting circuit may possibly erroneously detect that the oscillation is stopped.
Furthermore, the circuit disclosed in Japanese Patent Application Laid-open No. 2000-332585 has the following disadvantages. In the clock or the other electronic device, a transient period after the power is turned on before the clock or the other electronic device is turned into a stable state is normally an unstable period in which potentials of the respective units of the circuits, a current carried across the respective units, and the like are unstable. In the unstable period, currents in current amounts different from those in the stable state are carried to the constant-current source and the current-mirror circuit. For example, if the discharge current is excessively carried, the oscillation detecting circuit may perform an unfavorable operation such as an erroneous detection of the oscillation stop although the oscillation is continued.
Moreover, with the configuration in which the constant-current source and the P-channel MOS transistors connected to the capacitor in parallel are used as the capacitor discharging units (see FIG. 12), the oscillation detecting circuit is required to considerably increase ON resistances of the P-channel MOS transistors connected to the capacitor in parallel so as to set the discharge time at the appropriate time. To do so, it is necessary to make a gate length of each P-channel MOS transistor large. This, in turn, disadvantageously increases a gate capacity of each P-channel MOS transistor. Accordingly, an operation of the constant-current source is made slow when the oscillation is started. The electronic device including the oscillation detecting circuit disadvantageously takes a longer time before it is started.